As semiconductor chips become increasingly dense, i.e. include a greater number of circuits per given area, it becomes increasingly difficult to provide adequate packaging for these chips. Such packaging must provide, for example, efficient and reliable interconnections for power distribution and internal and external signals, and adequate cooling to prevent overheating. Further, these packages must be small in size, economic to manufacture, and reliable in operation.
The problem of high-density, high-performance packaging has been addressed in a variety of manners, several of which are discussed below.
U.S. Pat. No. 4,466,181 to Takishima shows a package wherein multiple semiconductor chips are conjoined at the edges such that the surfaces supporting wire connectors are planar. The conjoined chips are mounted in a recess of a wiring board such that the planar chip surfaces are level with the surface of the wiring board. Conductors are then formed on the surface of the package to interconnect the chips with each other and with the wiring board. Takishima suffers from at least the one disadvantage that edge joining of chips is difficult at best and not practically applicable with respect to large numbers of chips.
U.S. Pat. No. 4,630,096 to Drye et al. shows a variety of chip packages or modules. FIG. 1 of Drye et al. shows a package wherein chips are set in the of a printed circuit board, and connected to wiring planes on the board by bonding wires. FIG. 3 of the patent shows a package wherein chips are set in recesses in a substrate and connected to wiring patterns on the substrate by bridge leads. FIGS. 4A-4D show packages wherein chips are mounted in through-holes of a silicon substrate and interconnected by planar metallization. FIGS. 6 and 7 show the packages of FIGS. 4 further mounted in a sealed package with connecting pins. These later embodiments shown in FIGS. 4, 6, and 7 suffer from. the disadvantage of the difficulties inherent in connecting electrical pins to a silicon substrate, making the package impractical for high-performance applications.
U.S. Pat. No. 4,578,697 to Takemae shows a package including a ceramic substrate having conductive strips situated thereon. Chips are fastened to the substrate so as to be insulated from the conductive strips. Connectors on the chips are bonded to the conductive strips by wires.
Ehret, P., et al., MULTICHIP PACKAGING, IBM Technical Disclosure Bulletin, Vol. 14, No. 10, Mar. 1972, pg. 3090, shows a package wherein chips connected by solder-ball bonds to a multilevel wiring substrate are sandwiched between the substrate and a heat sink. Pins extending through the heat sink are used to make electrical connections to the multilevel wiring substrate.
Motika, F., FLIP-CHIP ON PERSONALIZATION CHIP CARRIER PACKAGE, IBM Technical Disclosure Bulletin, Vol. 23, No. 7A, Dec. 1980, pgs. 2770-2773 shows a package wherein multiple chips are solder-ball bonded to a personalization chip. The personalization chip is joined to a pin-supporting ceramic substrate, and connected to the pins by a special type of edge joint or chip.
Bodendorf, D.J., et al., ACTIVE SILICON CHIP CARRIER, IBM Technical Disclosure Bulletin, Vol. 15, No. 2, July 1972, Pgs. 656-657, shows a package wherein small silicon chips supporting active FET devices are mounted on a larger silicon chip supporting active bipolar devices. The connections between the small and large silicon chips are made via a planar, multi-level metallurgy.
It is further known in the art to utilize multilayer ceramic (MLC) packages for semiconductor chips. Such packages are shown, for example, in U.S. Pat. Nos. 4,245,273 to Feinberg et al. and 4,080,414 to Anderson et al. (both assigned to the assignee of the present invention and incorporated herein by reference). These packages, however, typically require the use of solder-ball connections between the chips and the packages. This solder-ball technology is complex in nature. It requires that all of the power, ground, and signal interconnections be contained within the multi-layers of the MLC package. This can result in a complex, expensive package.